Metals can be machined at a microscopic level to produce small pieces. Micromachining for metal cutting has been thoroughly reviewed in this article. Understanding the mechanical behaviour of a specific material is critical to the success of party manufacturing. Material removal in micromachining and conventional machining is significantly different due to scale effects on tool geometry and workpiece materials. As a survey of recent microtool designs, materials, and fabrication methods, this work is presented. The effectiveness of Carbide tools is discussed, as well as new methods and strategies. The machining of hard materials and the accompanying process factors, such as internal cooling and surface patterning techniques, are of particular interest in this regard. The assessment concludes with proposals for an integrated design and fabrication process chain that can assist industrial microtool manufacturing.

Keywords : Hard materials, Carbide tools, Micromachining

Author : V.S Ramprasad Nalamati, Dr.S. Chakradhar Goud

Title : A REVIEW ON MICROMACHINING OF HIGH STRENGTH MATERIALS WITH CARBIDE TOOLS

Volume/Issue : 2019;01(3)

Page No : 222-228

Phase Locked Loop (PLL) is a closed loop, negative feedback system. A closed-loop feedback control system, which synchronizes its output signal in frequency as well as in phase with an input signal, is PLL. The phase detector, loop filter, and the voltage controlled oscillator are the key parts of almost all PLLs. This paper gives investigation study of various PLL works suggested by some researches for low power and performance applications. Also, an attempt of understanding different technologies and reviewing the different methods of designing a low power PLL has been made. In this paper survey on different types of Phased locked loop techniques for low power and high performance applications is presented. Firstly the general structure of PLL is explained briefly then some of the PLL techniques which are focused on low power and high performance can be studied. Then all circuits that are studied will be compared and a result analysis can be performed. From the result analysis it can be found that the Digital Phased Locked Loop (DLL) have result in good phase noise performance with low power consumption with improved tuning range as compared to other phased locked loop circuits, as it uses the CMOS technology providing the real solution in the band of radio frequency. It is used in various applications such as wireless sensor network, transceiver, Clock generations, clock recovery circuits etc.

Keywords : Phase Locked Loop (PLL), phase detector, loop filter, voltage controlled oscillator (VCO), Digital phased locked loop (DLL).

Author : GUVVALADUNNE PRASANNA KUMAR, Dr VIJAY PRAKAH SINGH

Title : SURVEY ON PHASE LOCKED LOOP AND DIGITAL PHASED LOCKED LOOP

Volume/Issue : 2019;01(3)

Page No : 232-241

In This Article, Automated system and different taxonomies, the growth of the plant can be monitored. This type of information will be useful to farmers, botanists, and food engineers. In this article we combine Image Processing and the Internet of Things to monitor plant growth and collect climatic factors such as humidity and temperature. In image processing, there is a recognition system that detects the growth of plants using the images of their leaves, so the use of pesticides can be controlled. The system compares the image with those in the database, executing the pre-processing and feature extraction technique to obtain possible matches. In this method we extract the color, texture and shape of the leaf. Based on pattern recognition, a leaf can be identified as healthy or unhealthy. The first sensors are activated, with the help of the cameras, the image is captured and stored for future improvements. After identifying crop diseases using the various imaging techniques, alerts can be sent to farmers. The farmer can see the status of his field even sitting at home using web or mobile applications.

Keywords :

Author : Madugula Kranthi Kumar,Dr Hare Krishna

Title : A Survey Paper on Plants Using IOT

Volume/Issue : 2019;01(3)

Page No : 242-245

Energy conservation is one of the most significant design issues in wireless sensor networks. In this work, we propose an energy efficient routing algorithm which aims to maximize the lifetime of the network by minimizing the energy consumption of the nodes, is proposed. we propose an energy-proficient hub planning rebunching calculation of groups and pivoting bunch head positions to equitably scatter the energy load with a significant number of the hubs by the hub booking thought of hub actually dynamic and rest framework in each heterogeneous and homogeneous answers for get an energy-saving outcome. Our proposed thing is really improved from LEACH convention by adjusting hub planning program (dynamic and rest) in heterogeneous and homogeneous hub geographies of WSNs, which yield better execution in energy saving and afterward further developed organization lifetime. This specific hub booking program is fittingly carried out, and results demonstrate that the proposed plan of our own is really giving expanded energy effectiveness and drags out the lifetime of WSNs.

Keywords : Wireless Sensor Networks, LEACH, Organization Lifetime, Dynamic And Rest.

Author : Doddavarapu Sreenu Babu, Dr. Vijay Prakash Singh

Title : An Improved Energy Efficient Routing in Wireless Sensor Networks

Volume/Issue : 2019;01(3)

Page No : 246-252

Speaker recognition is essential in the field of authentication and surveillance to validate the identity of the user using the extracted features of the audio speech signal. A novel Delta Coefficients-based Bacterial Foraging Optimization (BFO) with Radial Basis Function (RBF) for identification of exact speaker is proposed in this paper. The speaker recognition function can be done with two modules, namely Training and Testing. Initially throughout the training step, the Delta Coefficients of each speech sample are derived by pre-processing the audio speech signal. Then the features are classified towards the target speaker using RBFNN. Bottleneck features for abstract representation are extracted in RBFNN and the dimensionality by Principal Component Analysis (PCA) is further decreased. To improve the classification accuracy, the features are optimized with Bacterial Foraging optimization (BFO) algorithm. Finally, the probability score for each speaker is generated to identify the speaker. The proposed Delta Coefficients based BFO using Bottleneck features (DBFOB) method is evaluated with TIMIT data corpus. The improved performance is presented with regard to Equal Error Rate (EER).

Keywords : Speech processing, speaker recognition, RBF neural network, and Bacterial foraging optimization, scoring

Author : P S Subhashini Pedalanka. Dr M. SatyaSai Ram,Dr Duggirala SreenivasaRao,

Title : Delta Coefficients based Bacterial Foraging Optimization with RBF Neural Network for Speaker Recognition

Volume/Issue : 2019;01(3)

Page No : 253

This paper offers an account of the past as recollected in the form of presence with an emphasis on the interiority of experience as articulated in Anita Desai's novels. As we know experience in general means the understanding of or skill of something or some event that is gained through participation in or exposure to that thing or event. If a person has exposure to a particular field with considerable experience, he/she can be called to be an expert in that field. We as human beings undergo a lot of experiences in our day-to-day life. Depending on the situation, the experience can be physical, social, emotional, spiritual, etc. Similarly, the characters in the fiction of Anita Desai undergo many experiences in their day-to-day chores. The central concern of this paper is to analyze how Anita Desai has delved into the inner selves of the characters through her creative spirit. In addition to this, the chapter also highlights how the past is recollected in the form of the present. In order to establish this, adequate attention is paid to the details of the texts.

Keywords : Anita Desai's novels, Interiority of Experience, Experiences, Physical, Social, Emotional, Spiritual

Author : SHASHIDHAR YADRAMI, Dr.VIBHA GUPTA

Title : The Past as Recollection in the Form of Presence: The Interiority of Experience

Volume/Issue : 2019;01(3)

Page No : 260-265

This paper introduces certain key aspects of the major regionalist movements in postIndependence India, perhaps strike a dissonant note in relation to the rest of this dissertation, and might be read as a loosely strung but necessary intermezzo. Rather than impose a false coherence on historically discontinuous material, we have chosen to retain the sense of prickliness and jaggedness characteristic of the available (textual) archives that document the histories of the regionalist struggles against the Indian State. Presenting this information, not all of which can be presumed to be widely familiar, is however a necessary prelude for emphasizing (1) the importance and magnitude of the "regional problem" in post-Independence India, and (2) the the complex political backdrop against/towards which any re-concept utilization of the regional question must find its theoretical mornings.

Keywords : Regionalist Moments, Indian State, Post-Independence, Period

Author : RAGHVENDRA S, Dr.VIBHA GUPTA

Title : Regionalist Movements in the Post-Independence Period

Volume/Issue : 2019;01(3)

Page No : 266-270

The task for identifying the right mutual fund schemes and deliver excess returns over the benchmark index is a central issue for the financial academics. Certainly, the financial academics have always been devoted to develop an objective and accurate measure, which is able to assess and compare the performance and judge the abilities of the fund managers. This need has emerged out of two different dimensions. On one hand, the investors are interested to find out if the fees and expenses incurred by them are justifiable and on the other hand, the fund managers would like to reveal their importance and justify the importance of actively managed over passively managed portfolios. Consistent with a steady growth of the mutual fund industry worldwide, there is a great deal of work conducted towards the development of more sophisticated measures on performance measurement. Thus, in this chapter, a popular risk-adjusted performance measure is presented, which is used to evaluate the performance of the selected open-ended mutual fund schemes and to identify if the fund managers have superior stock selection abilities.

Keywords :

Author : PRABHAKAR ISHWARAPPA, Dr.J.HALDER

Title : OPEN-ENDED MUTUAL FUND SCHEMES IN INDIA BASED ON PERFORMANCE OF SELECTIVITY

Volume/Issue : 2019;01(3)

Page No : 271-276

This paper is an attempt to uncover the hidden meanings of the poetry of Kamala Das from the perspective of women and from the angle of self-reflections of herself in her works. This paper is a kind of exploration of her poetry. The various themes include the feminine approach, man-woman relationships, Love, lust, and different threads of human life which bind two opposite sexes in one relationship. This journey in her works depicts all sensory experiences which have a definite bridge between man and woman. Her writing is not only a reflection of real society but her work gives insight into the knowledge of man-woman relationships' psychology also.

Keywords :

Author : VANI S, Dr. DHANUKUMAR ANGADI

Title : ANALYSIS OF SUMMER IN CALCUTTA BY KAMALA DAS

Volume/Issue : 2019;01(3)

Page No : 277-280

Static Random Access Memory (SRAM) has become a major component in many VLSI Chips due to their large storage density and small access time. SRAM has become the topic of substantial research due to the rapid development for low power memory design during recent years due to increase demand for notebooks, laptops, IC memory cards and hand held communication devices. SRAMs are widely used for mobile applications as both on chip and off-chip memories, because of their ease of use and low power consumption. In the performance of memory cell, delay and power consumption plays a major role. Random-Access Memory employs latching circuitry to store data and preserve the bits MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) help compensate for the SRAM cells. In addition, improvements withinside the System of Chip are essential. In this work, a novel design and implementation of 7T SRAM array with 28 nm technology using SVL (self-controllable Voltage Level) method is presented. The main objective of this work is to reduce the leakage power of SRAM array. The SVL method is used to analyze the consumption of power, leakage power and current parameters of 7T (7- Transistor) SRAM array.

Keywords :

Author : SHAIK NANNU SAHEB, Dr .RAMESH MARPU, Dr.PRABODH KHAMPARIYA

Title : A NOVEL DESIGN AND IMPLEMENTATION OF 7T SRAM ARRAY WITH 28 NM TECHNOLOGY USING SVL METHOD

Volume/Issue : 2019;01(3)

Page No : 281-288

In this digital age of communication, private and confidential data is exchanged over the internet and stored in digital mediums. Cryptography is one of the techniques to protect sensitive data. Cryptographic techniques are the one that have been implemented to enhance the data security level in all such communication systems. The symmetric cryptographic technique of Advanced Encryption Standard (AES) is considered suitable for this security enhancement. This standard has become one of the most widely used encryption methods and has been implemented in both software and hardware. Hardware implementation would be faster and more secure as compared to software implementation. However, Field Programmable Gate Arrays (FPGA) implementation offers quicker solution and can be easily upgraded to incorporate any protocol changes. This research investigates high-performance FPGA architecture of AES encryption for secured cryptography. High-performance AES encryption is designed and implemented in FPGA, which is shown to be more efficient in terms of speed and area. This paper provided a guideline for the implementation of a more secure way with cryptographic algorithm of AES.

Keywords :

Author : JAYASHREE CHAVAN, Dr.AMIT JAIN

Title : HIGH PERFORMANCE FPGA ARCHITECTURE OF AES ENCRYPTION FOR SECURED CRYPTOGRAPHY

Volume/Issue : 2019;01(3)

Page No : 289-294

The means of distributing the everchanging load by properly scheduling the available units, both thermal and solar photovoltaic(PV) units of distributed generation so as to obtain the most economic operating cost, reducing the valve point loading effects, minimizing the emissions and making the maintenance of the units simpler is proposed in this paper. The analysis carried out on 6,15,31Thermal units without and with integration of solar PV units distributed at uniform geographical locations in the state of Telangana, India. The unique cost -per -hour characteristics of thermal generating units(TG), their emissions, valve point loading effects, ramp rate limits, prohibited operating zones and capacity constraints make the cost equation more complex also the cost of operation of thermal units is more.To supply for reliable, sustainable,ever increasing load requirements in most economical way, solar power plants have to be installed and integrated them to the grid evenly across various geographical locations in addition to the already existing ones. The allocation of the load i.e the Load Dispatch to the generating units both Solar PV and TG considering their various parameters which effect their cost of operation are evaluated for different load demands to obtain the most economical operating costs using the 3 algorithms, viz., Non-linear Generalized reduced gradient (GRG) algorithm, Evolutionary algorithm(EA) and Moth flame optimization algorithm (MFA) and the results are compared. While calculating ELD,the various parameters such as the fuel cost coefficients, valve point loading effects, penalty due to emissions, transmission losses, minimum and maximum capacities, ramp rate limits and prohibited operating zones of thermal power units and the parameters such as the minimum, maximum and average power capacities of a solar PV units placed at that particular location,which in turn depend on the solar irradiance values for the peak solar hours in any day of the year at that location and a factor of overestimation, underestimation of available solar power of PV units are considered. By integrating PV units with Thermal units, the transmission line losses, the cost incurred due to valve point loading effects, the penalties due to emissions, and mainly cost of load dispatch which is associated to all the aboveare greatly reduced more so in case of systems having lager number of units and with greater power demand.Even the maintenance of TG units becomes simpler as the loads are distributed to PV units. Non-Linear GRG and Evolutionary algorithm are simpler and can be evaluated in Solver an add-in ofMicrosoft Excel inMSOffice2010 version and above systems and consume less time and needs only a minimum coding knowledge.Also,the results obtained from MFA are more economical compared to Evolutionary algorithm and GRG algorithm andthe time taken for convergence to arrive at Global optima is also very less.

Keywords :

Author : Sridevi Pusapati,andRavindranath Reddy B.

Title : Economic Load Dispatch of Distributed Generation – An analysis of Thermal units with and without integration of PV units.

Volume/Issue : 2019;01(3)

Page No : 295-308

This paper utilizes the discrete wavelet method to display an in-depth study of three standard and two level convolved DC to DC converters. DC to DC adapters are becoming more and more important in a variety of application areas, including biomedicine, manufacturing, and household. owing to their incredible talent to magnify the voltage level to meet the demands of the preferred load voltage. However, ability to handle an elevated input signal when trying to design an output power inverters for high voltage applications is a significant challenge. The overlapping converter is the best power converter topology for small photovoltaic modules because of its higher efficiency, compact size, present sharing between levels, low input power ripple, and higher reliability. Using the discrete wavelet method, the achievement of the three - stage proposed converter is especially in comparison to that of the two level interleaved boost source inverterThe results of the simulation study, which was conducted in the MATLAB SIMULINK environment, are in good agreement with previously published research.

Keywords :

Author : P. Krishna Murthy, A.K.Srikanth, S. Neelina

Title : DESIGN AND ANALYSIS OF WAVELET TRANSFORM TECHNIQUE BASED INTERLEAVED BOOST CONVERTER

Volume/Issue : 2019;01(3)

Page No : 309-314