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HIGH PERFORMANCE FPGA ARCHITECTURE OF AES ENCRYPTION FOR SECURED CRYPTOGRAPHY
In this digital age of communication, private and confidential data is exchanged over the internet and stored in digital mediums. Cryptography is one of the techniques to protect sensitive data. Cryptographic techniques are the one that have been implemented to enhance the data security level in all such communication systems. The symmetric cryptographic technique of Advanced Encryption Standard (AES) is considered suitable for this security enhancement. This standard has become one of the most widely used encryption methods and has been implemented in both software and hardware. Hardware implementation would be faster and more secure as compared to software implementation. However, Field Programmable Gate Arrays (FPGA) implementation offers quicker solution and can be easily upgraded to incorporate any protocol changes. This research investigates high-performance FPGA architecture of AES encryption for secured cryptography. High-performance AES encryption is designed and implemented in FPGA, which is shown to be more efficient in terms of speed and area. This paper provided a guideline for the implementation of a more secure way with cryptographic algorithm of AES.
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