Article
SURVEY ON PHASE LOCKED LOOP AND DIGITAL PHASED LOCKED LOOP
Phase Locked Loop (PLL) is a closed loop, negative feedback system. A closed-loop feedback control system, which synchronizes its output signal in frequency as well as in phase with an input signal, is PLL. The phase detector, loop filter, and the voltage controlled oscillator are the key parts of almost all PLLs. This paper gives investigation study of various PLL works suggested by some researches for low power and performance applications. Also, an attempt of understanding different technologies and reviewing the different methods of designing a low power PLL has been made. In this paper survey on different types of Phased locked loop techniques for low power and high performance applications is presented. Firstly the general structure of PLL is explained briefly then some of the PLL techniques which are focused on low power and high performance can be studied. Then all circuits that are studied will be compared and a result analysis can be performed. From the result analysis it can be found that the Digital Phased Locked Loop (DLL) have result in good phase noise performance with low power consumption with improved tuning range as compared to other phased locked loop circuits, as it uses the CMOS technology providing the real solution in the band of radio frequency. It is used in various applications such as wireless sensor network, transceiver, Clock generations, clock recovery circuits etc.
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