Article

A NOVEL DESIGN AND IMPLEMENTATION OF 7T SRAM ARRAY WITH 28 NM TECHNOLOGY USING SVL METHOD

Author : SHAIK NANNU SAHEB, Dr .RAMESH MARPU, Dr.PRABODH KHAMPARIYA

Static Random Access Memory (SRAM) has become a major component in many VLSI Chips due to their large storage density and small access time. SRAM has become the topic of substantial research due to the rapid development for low power memory design during recent years due to increase demand for notebooks, laptops, IC memory cards and hand held communication devices. SRAMs are widely used for mobile applications as both on chip and off-chip memories, because of their ease of use and low power consumption. In the performance of memory cell, delay and power consumption plays a major role. Random-Access Memory employs latching circuitry to store data and preserve the bits MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) help compensate for the SRAM cells. In addition, improvements withinside the System of Chip are essential. In this work, a novel design and implementation of 7T SRAM array with 28 nm technology using SVL (self-controllable Voltage Level) method is presented. The main objective of this work is to reduce the leakage power of SRAM array. The SVL method is used to analyze the consumption of power, leakage power and current parameters of 7T (7- Transistor) SRAM array.


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