Leakage power has emerged as a critical concern in
VLSI design due to the relentless scaling of transistor dimensions
and increasing transistor count on integrated circuits. As
technology nodes continue to shrink, leakage power has become a
dominant component of the overall power consumption, leading
to performance degradation, reduced battery life, and increased
heat dissipation. This review paper provides a comprehensive
analysis of leakage power in VLSI design, focusing on its sources,
challenges, and potential solutions. Various techniques for
leakage power reduction at the circuit and architecture levels are
discussed, including power gating, multi-threshold voltage
techniques, supply voltage scaling, and process optimizations.
Additionally, leakage power models and estimation methods are
explored, along with trade-offs and design challenges associated
with leakage power reduction. The paper also presents case
studies and experimental results to illustrate the effectiveness of
leakage power reduction techniques in practical designs. The
insights provided in this review paper will aid researchers and
practitioners in understanding the complexities of leakage power
and making informed decisions during VLSI design to mitigate
its adverse effects.
Keywords : VLSI design, leakage power, power gating, multithreshold voltage, supply voltage scaling, process optimization, power consumption
Author : Mrs.M. Balram
Title : Addressing Leakage Power in VLSI Design: Strategies, Trends, and Future
Volume/Issue : 2023;05(06)
Page No : 1 - 4
