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Static Random Access Memory with Half Vdd and Dynamically Powered Read Port for High Speed and Low Switching Power Capabilities
In this paper, we introduce a 10-transistor static random access memory cell that features an unbalanced read decoupled bit line (RBL) with a 4T read pin for high-speed operation. Based on the stored data bit, the RBL is pre-charged to half the cell's supply voltage and allowed to charge and discharge. The Complementary Data (QB) node is driven by an inverter that connects the RBL to the virtual power rails via a transmission gate during read operation. RBL rises to VDD level for a read of 1 and dumps to ground level for a read of 0. During write mode and standby mode, the virtual power rails have the same RBL precharge level value. During the reading process, these are connected to actual supply levels. Dynamic control of virtual rails significantly reduces RBL leakage. The proposed 12T cell is larger compared to the SRAM 10T and reduces read lag by more than 50% compared to the 10T. The general performance characteristics of the 12T and 10T are similar, and the general designs are designed and implemented at Tanner EDA.
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