An Efficient Novel Approach Paradigm of Single Cycle Switching Access Structure to Eliminate the Peak Power Consumption Problem
Now a day’s the Conventional shift-based scan chains have the drawback of peak power consumption which is reduced by the proposed single cycle access test structure for logic test. With theMost efficient reduction of this power consumption the activity during shift and capture cycles have been achieved. In addition, more accurate circuit behavior can be achieved even at stuck-at and at-speed tests using the proposed methodology. Thereby it accomplishes close proximity to the functional mode during higher frequency operation tests.By using the proposed design minimum number of test cycles can be gained to the existed literature. It is observed that test cycles per net is below 1 for larger designs when tested for simple test pattern generator algorithm without test pattern compression. Has the advantage of independent of the design size and also provides an additional on-chip debugging signal visibility for each register. It is backward compatible to the standard full scan designs and with a minor enhancementexisting test pattern generators and simulators can be used and also discussed for the solution of adding built-in self test (BIST) and massive parallel scan chains with the proposed design.The design and implementation of single cycle access test structure for logic test is functionally verified using Xilinx ISE simulator 13.1 and the generated bit stream file is implemented in Spartan 3E XC3S50OE FPGA board, which demonstrates the all-possible combinations of proposed single cycle access test structure for logic test on its LCD display. The pre layout and post layout synthesis and its physical design are performed using cadence RTL Compiler and SOC Encounter tools respectively, with the optimized area, power, and delay.
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