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		<www.wjpsonline.org>
		<Title>CMOS/VLSI Circuit for Power Optimization on Portable Devices </Title>
		<Author>Kurapati Divya</Author>
		<Volume>02</Volume>
		<Issue>1</Issue>
		<Abstract>In this day and age utilizing convenient gadgets are chiefly being used which turned out to be every day need in our lifes in which control utilization is principle situation which requests low power This should be possible with procedures and principles while planning To build control utilization through VLSI innovation CMOS NMOS PMOS Transistor circuits are utilized and the submicron innovation likewise utilized for the prerequisite of low power gadgets increments altogether Spillage current and power dispersal in both static and dynamic must be thought about which can bother the gadget execution This paper presents strategies to lessen the power scattering and different philosophies to expand the speed of gadget This can be useful in future low power innovation</Abstract>
		<permissions>
<copyright-statement>Copyright (c) World Journal of Pharmaceutical Seiences. All rights reserved</copyright-statement>
<copyright-year>2026</copyright-year>
</permissions>
		</www.wjpsonline.org>
		